Using Sacks to Organize Registers in VLIW Machines

This paper analyses the register requirements of software pipelined inner loops. When the number of functional units and/or the number of stages of individual functional units is increased, the number of registers required may be prohibitive in chip area and cycle time. We characterize lifetime of values in pipelined loops with their loop register locality (LRL). Based on this characteristic, we propose a new organization of the register le in order not to aaect cycle time and also reduce area, while increasing the number of registers. This can be useful to minimize the frequency of spill at a reasonable cost. The spill code can increase the minimum initiation interval and decrease loop performance. This new organization consists of a small high bandwidth multiported register le and a low bandwidth port-limited register le called sack. A mechanism to assign values to the sack is presented. We demonstrate the eeectiveness of our approach by experimenting with a collection of loops from the Perfect Club benchmark suite. Experiments in order to nd the optimal number of registers into the sack have been done. We also measured the eeect of the spill code on loop performance.